The present invention relates to power switching devices. More specifically, the present invention provides improved techniques for switching between high and low side devices in a half-bridge configuration.
Conventional integrated circuit half-bridge drivers typically use non-overlapping power MOSFET gate control signals to guarantee a minimum time interval when both high side and low side power MOSFETs are in a high impedance state. This interval is commonly referred to as the `dead time`. The dead time interval occurs just prior to the commutation of current from one switching device to the other and is needed to ensure that there is no simultaneous conduction of current through the two switching devices, i.e., no shoot-through current. The dead time interval must often be larger than desired to insure that a minimum dead time is maintained over IC operational temperatures and process variations.
During the dead time, when both power switching devices are high impedance, any output current flowing in an inductive load is forced to flow through the parasitic body diode of either the high or low side switching device. When the half-bridge driver and power MOSFETs share the same silicon substrate, current flowing through the body diodes of the power MOSFETs can activate additional parasitic transistors on the IC substrate. Activation of these parasitic transistors can be an unwanted source of power dissipation and can interfere with the normal operation of the half-bridge control circuitry. Moreover, activation of these parasitic transistors can even destroy the IC via a well known mechanism known as latch-up.
A common solution to this problem is to add external Schottky diodes in parallel with the power MOSFET body diodes. The external Schottky diodes, having a lower forward voltage, then carry most of the current that would otherwise flow in the body diodes during the dead time. However, series inductance associated with the Schottky diodes and the half-bridge IC packaging often limits the effectiveness of this technique when switching large currents at high frequencies. This solution also adds considerable cost to a system and is thus undesirable.
FIG. 1 of the drawings illustrates the prior art half-bridge switching power amplifier. V1 and V2 are typically 5V to 10V voltage sources. The gates of power MOSFETs M1 and M2 are driven such that there is a time interval when both M1 and M2 are off and not conducting current. This time interval has been referred to herein as the dead time. During the dead time, when current is flowing into or out of the switching power amplifier output due to an inductive load, one of the body diodes D1 or D2 conducts the current. This causes the output to rise above VDD or fall below GND by an amount determined by the forward voltage of the body diode.
The gate drive, output voltage and output current waveforms for the switching power amplifier of FIG. 1 are shown in FIG. 2. FIGS. 3 and 4 are simplified illustrations of the two-step switching process for the half-bridge power amplifier in FIG. 1 according to the prior art. The gate switches from FIG. 1 have been removed for simplicity and the power MOSFETs are represented by their respective region-of-operation resistance. FIG. 3 shows the case where current is flowing into the amplifier output stage and FIG. 4 shows the case where current is flowing out of the amplifier output stage.
FIGS. 3a through 3c show the three states of the switching process for the half-bridge power amplifier in FIG. 1 for the case where current is flowing into the amplifier output stage, i.e., interval t0-t5 in FIG. 2. In FIG. 3a, load current is flowing into M2 with M2 acting as a switch conducting the current to GND (State 1). The first step of the conventional switching process is to discharge the gate of M2 completely. This causes both output MOSFETs to be in a high impedance state as shown in FIG. 3b (State 2). During this dead time (interval t1-t2 of FIG. 2), the output current remains relatively constant and therefore flows almost entirely through D1 back into the power supply VDD. As can be seen in FIG. 2, the voltage drop across D1 causes the output voltage Vout to rise above VDD during this interval. The second step of the switching process is to charge the gate of M1 which then diverts the current from D1 as shown in FIG. 3c (State 3). The sequence 3a-3b-3c illustrates the output voltage transitioning from low to high. The process is reversible for the case when the output voltage is transitioning from high to low, i.e., 3c-3b-3a.
FIGS. 4a through 4c show the three states of the switching process for the half-bridge power amplifier in FIG. 1 for the case where current is flowing out of the amplifier output stage, i.e., interval t5-t9 in FIG. 2.
Body diode conduction of IC power devices during conventional switching can have catastrophic consequences for the IC. It is therefore desirable to provide techniques by which switching of a half-bridge configuration may be accomplished while minimizing the current conducted by the body diodes of the power devices.